November 10, 2003 2:48 PM PST
Open-and-shut case for new transistor gates?
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Intel puts Tri-Gate transistor on fast track
June 10, 2003
Researchers at the company's Austin, Texas, laboratory said Monday that they have developed a dual-gate transistor in which the two gates can act independently, a first according to the company. Ideally, this will simultaneously increase performance and reduce power consumption.
Dual- and triple-gate transistors are one of the many design concepts semiconductor manufacturers hope to integrate into chips in the next decade. A transistor is a microscopic on-off switch inside a chip that--depending on whether a gate is allowing electricity to pass through it--is read as a one or a zero by the computer.
Most multiple-gate transistors are being proposed as a way to offload the drive current, the amount of electricity required to operate a semiconductor, onto a greater number of circuits. Increasing drive current increases performance, but it can also exacerbate problems like electrical leakage that can outweigh any benefits. In a rough analogy, chips with multi-gate transistors can get up to speed without overheating.
In most multi-gate proposals, the transistor gates act in concert. In Motorola's Multiple Independent Gate Field Effect Transistor (MIGFET), the transistor gates are electrically isolated, so they can work together, or function like independent transistors, depending on the chip designer's intent. This could lead to a wider variety of options for increasing performance and reducing power consumption. Complex calculations that require millions of transistors, for instance, can be performed on half as many transistors, according to Motorola.
"It may give them some flexibility," said Kevin Krewell, senor editor of The Microprocessor Report. "One of the purposes of double and triple gates is to increase current."
Motorola did not commit to when such transistors could be included in their processors, but different manufacturers have said that enhancements like this could emerge with the 45-nanometer manufacturing process, which is expected to debut in 2007 or 2008.
"The process techniques being introduced are independent of wafer size and process geometry, and have been successfully demonstrated on existing production technologies," Claudine Simson, chief technology officer, Motorola's Semiconductor Products Sector, said in a statement. Motorola plans to continue to work on refining these advanced devices and incorporate them in a variety of process technologies and product lines."
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