November 27, 2002 5:38 AM PST
"Hammer" to hold 100 million transistors
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A chip with that many transistors is currently considered unusual. But when Hammer chips emerge in the first half of 2003, processors of that complexity will become increasingly common. That's because designers are increasing the size of caches, which are reservoirs of memory located on the processor for rapid data access, and adding other features.
Details of AMD's forthcoming chip have been leaking out. The largest version of Hammer, for instance, will have 1MB of secondary cache, as well as an integrated memory controller for connecting the processor to a PC's memory, according to the company. Currently, memory controllers mostly sit on their own piece of silicon.
Hammer is a "100 million transistor machine," CEO Hector Ruiz said in a recent interview. AMD chief scientist Bill Siegel, meanwhile, said recently at the company's analyst meeting that the chip will have about 2.5 times as many transistors as the current Athlon chip. The Athlon has about 38 million transistors, so by Siegel's count the total for Hammer would be approximately 95 million. The company would not provide a specific number.
The chip will debut at around 2GHz and come out with a performance rating number in the mid-3,000s, added Dirk Meyer, senior vice president of AMD's computational products group. Current Athlon performance ratings top out at 2,800. The ratings correspond roughly to the speed of Intel chips, so an AMD Athlon XP 2800+ would perform like a 2.8GHz Intel Pentium 4.
The 1MB version--the chip that will contain 100 million transistors--will mostly be sold into servers and be marketed under the Opteron name, sources say. A smaller version with 256KB or more of cache and an integrated memory controller will be marketed to desktops under the Athlon 64 name.
Other chips with large caches and a high number of transistors include Banias, the code name of a notebook chip coming from Intel in the first quarter. Banias will contain 77 million transistors and 1MB of cache. The current Intel Pentium 4 sports about 54 million transistors.
While a greater number of transistors generally leads to better performance, chips with large transistor budgets are also expensive and often difficult to manufacture. AMD and Intel will be competing over who can produce the cheapest chips. AMD has vowed that its chips will be the smallest, giving it an advantage in costs.
Right now, the ultimate winner is tough to call. The 1MB version of Hammer will likely sport a surface area of 180 square millimeters, said Kevin Krewell, managing editor of industry newsletter Microprocessor Report. The smaller version for desktops will take up around 105 square millimeters.
Intel's current Pentium 4 and Xeon chip for workstations take up 146 square millimeters of area, according to Intel. These chips contain 512KB of cache. A Xeon with 2MB of cache takes up 268 square millimeters.
The dimensions listed above, however, apply when the chips are manufactured on the 130-nanometer process. In the second half, Intel will begin to produce chips on the 90-nanometer process, which will shrink the size considerably. The nanometer figures refer to the average size of features on the processor; there are 1 billion nanometers in a meter.
By then, the current Pentium 4 will drop to 105 square millimeters. A new chip code-named Prescott, with undoubtedly even more transistors, will also emerge at the time.
AMD will begin to manufacture 90-nanometer chips at the tail end of 2003, but the company won't start selling them publicly until the first half of 2004, Meyer said.
At that rate, Intel will could have a six-month advantage when it comes to 90-nanometer production, Krewell speculated. Intel will also make chips on 300-millimeter wafers, a capability--which AMD doesn?t have internally--that further cuts costs.
